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January 2007
HYS64D 64020H B DL - 5 - C HYS64D 64020G B DL - 5 - C HYS64D 64020H B DL - 6 - C HYS64D 64020G B DL - 6 - C
200-Pin Small Outline Dual-In-Line Memory Modules SO-DIMM DDR SDRAM
Internet Data Sheet
Rev. 1.21
Internet Data Sheet
HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
HYS64D64020HBDL-5-C, HYS64D64020GBDL-5-C, HYS64D64020HBDL-6-C, HYS64D64020GBDL-6-C Revision History: 2007-01, Rev. 1.21 Page All All Subjects (major changes since last revision) Qimonda update Adapted internet edition
Previous Revision: 2005-09, Rev. 1.2
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03292006-F1IB-1I3E
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
1
1.1
Overview
Features
* Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * RAS-lockout Supported tRAP=tRCD * All Inputs and Outputs SSTL_2 Compatible * Serial Presence Detect with E2PROM * Jedec Standard form Factor: 67.60 mm x 31.75 mm x 3.80 mm * Gold Plated Contacts
This chapter lists all main features of the product family HYS64D64020[H/G]BDL-[5/6]-C and the ordering information.
* Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules * Two ranks 64M x 64 Organization * JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) * Single +2.5 V ( 0.2 V) Power Supply and Single +2.6 V ( 0.1 V) Power Supply for DDR400 * Built with 256 Mbit DDR SDRAMs Organised as x 8 in P-TFBGA-60 Packages
TABLE 1
Performance
Part Number Speed Code Speed Grade Max. Clock Frequency Component Module @CL3 @CL2.5 @CL2 -5 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 Unit -- -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
1.2
Description
capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
The HYS64D64020HBDL-5-C and HYS64D64020GBDL-5- C are industry standard 200-Pin Small Outline Dual-In-Line Memory Modules (SO-DIMMs) organized as 64M x64. The memory array is designed with Double Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling
TABLE 2
Ordering Information
Type PC3200 (CL=3.0) HYS64D64020GBDL-5-C PC2700 (CL=2.5) HYS64D64020GBDL-6-C PC2700S-2533-0-Z Two ranks 512 MB SO-DIMM 32 MBit (x8) PC3200S-3033-1-Z Two ranks 512 MB SO-DIMM 32 MBit (x8) Compliance Code Description SDRAM Technology
TABLE 3
Ordering Information for RoHS Compliant Products
Product Type 1) PC3200 (CL=3.0) HYS64D64020HBDL-5-C PC2700 (CL=2.5) HYS64D64020HBDL-6-C PC2700S-2533-0-Z Two ranks 512 MB SO-DIMM 32 MBit (x8)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Compliance Code PC3200S-3033-1-Z
Description Two ranks 512 MB SO-DIMM
SDRAM Technology 32 MBit (x8)
Notes 1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components. 2. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "2033-0" means CAS latency of 2.0 clocks, RCD 1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
2
Pin Configuration
explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are
TABLE 4
Pin Configuration of SO-DIMM
Pin# Clock Signals 35 160 89 CK0 CK1 CK2 NC 37 158 91 CK0 CK1 CK2 NC 96 95 CKE0 CKE1 NC Control Signals 121 122 S0 S1 NC 118 120 119 117 116 RAS CAS WE BA0 BA1 I I NC I I I I I SSTL SSTL -- SSTL SSTL SSTL SSTL SSTL Chip Select Rank 0 Chip Select Rank 1 Note: 2-ranks module Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable Bank Address Bus 1:0 I I I NC I I I NC I I NC SSTL SSTL SSTL -- SSTL SSTL SSTL -- SSTL SSTL -- Clock Signal Clock Signal Clock Signal Note: ECC type module Note: Non-ECC type module Complement Clock Complement Clock Complement Clock Note: ECC type module Note: Non-ECC type module Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module Note: 1-rank module Name Pin Type Buffer Type Function
Address Signals
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Pin# 112 111 110 109 108 107 106 105 102 101 115 100 99
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 NC
Pin Type I I I I I I I I I I I I I I NC I NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address Bus 11:0
Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit based module Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Data Bus 63:0
123
A13 NC
Data Signals 5 7 13 17 6 8 14 18 19 23 29 31 20 24 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13
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Pin# 30 32 41 43 49 53 42 44 50 54 55 59 65 67 56 60 66 68 127 129 135 139 128 130 136 140 141 145 151 153 142 146 152 154 163 165 171 175 164 166
Name DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0
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Pin# 172 176 177 181 187 189 178 182 188 190 71
Name DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 NC
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC I/O NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL -- SSTL --
Function Data Bus 63:0
Check Bit 0 Note: ECC type module Note: Non-ECC module Check Bit 1 Note: ECC type module Note: Non-ECC module Check Bit 2 Note: ECC type module Note: Non-ECC module Check Bit 3 Note: ECC type module Note: Non-ECC module Check Bit 4 Note: ECC type module Note: Non-ECC module Check Bit 5 Note: ECC type module Note: Non-ECC module Check Bit 6 Note: ECC type module Note: Non-ECC module Check Bit 7 Note: ECC type module Note: Non-ECC module
73
CB1 NC
79
CB2 NC
83
CB3 NC
72
CB4 NC
74
CB5 NC
80
CB6 NC
84
CB7 NC
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Pin# 11 25 47 61 133 147 169 183 77
Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 NC
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I I I I I I I I I NC I I/O I I I AI PWR
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- CMOS OD CMOS CMOS CMOS -- --
Function Data Strobes 7:0
Data Strobe 8 Note: ECC type module Note: Non-ECC module Data Mask 7:0
12 26 48 62 134 148 170 184 78
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 NC
Data Mask 8 Note: ECC type module Note: Non-ECC module Serial Bus Clock Serial Bus Data Slave Address Select Bus 2:0
EEPROM 195 193 194 196 198 1,2 197 SCL SDA SA0 SA1 SA2
Power Supplies
VREF VDDSPD
I/O Reference Voltage EEPROM Power Supply
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Pin# 9,10,21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192
Name
Pin Type PWR
Buffer Type --
Function Power Supply
VDD
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Pin# 3,4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 Other Pins 199 85, 86, 97, 98, 124, 200
Name
Pin Type GND
Buffer Type --
Function Ground Plane
VSS
VDDID
NC
O NC
OD --
VDD Identification
Not connected
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TABLE 5
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
FIGURE 1
Pin Configuration Diagram 200-Pin SO-DIMM
TABLE 7
Address Format
Density 512MB Organization 64M x64 Memory Ranks 2 SDRAMs 32M x8 # of SDRAMs 16 # of row/bank/ columns bits 13/2/10 Refresh 8K Period 64 ms Interval 7.8 ms
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
3
3.1
Electrical Characteristics
Operating Conditions
TABLE 8
Absolute Maximum Ratings
This chapter lists the electrical characteristics.
This chapter contains the operating conditions tables.
Parameter
Symbol Min.
Values Typ. -- -- -- -- -- -- 1 50 Max.
Unit
Note/ Test Condition -- -- -- -- -- -- -- --
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
-0.5 -1 -1 -1 0 -55 -- --
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 -- --
V V V V C C W mA
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit.
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TABLE 9
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage EEPROM supply voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Values Typ. 2.5 2.6 2.5 2.6 2.5 -- 0.5 x VDDQ -- -- -- -- -- -- -- -- -- Max. 2.7 2.7 2.7 2.7 3.6 0 0.51 x VDDQ V V V V V V V V V V V V -- A A mA Unit Note1) / Test Condition
VDD VDD VDDQ VDDQ VDDSPD VSS, VSSQ VREF VTT
2.3 2.5 2.3 2.5 2.3 0 0.49 x VDDQ
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4) 5)
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71 -2 -5 --
VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6
1.4 2 5 -16.2
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
CK Inputs Input Differential Voltage, CK VID(DC) and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current Output Leakage Current
6) 5) 5)
5)7)
VIRatio II IOZ
8)
Any input 0 V VIN VDD; All other pins not under test = 0 V 9) DQs are disabled; 0 V VOUT
Output High Current, Normal IOH Strength Driver
VDDQ 9) VOUT = 1.95 V
16.2 -- -- mA VOUT = 0.35 V Output Low Current, Normal IOL Strength Driver 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V; VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400);
2) 3) 4) 5) 6) 7) 8) DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin.
9)
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3.2
Current Specification and Conditions
TABLE 10
IDD Conditions
Parameter Operating Current 0 One bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. Operating Current 1 One bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current All banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; Address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current One bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current One bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle. Operating Current Read One bank active; Burst Length = 2; reads; continuous burst; Address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write One bank active; Burst Length = 2; writes; continuous burst; Address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 Four bank interleaving with Burst Length = 4; see component data sheet.
Symbol
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
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TABLE 11
IDD Specification for HYS64D64020[G/H]BDL-5-C
Product Type Organization HYS64D64020GBDL-5-C HYS64D64020HBDL-5-C 512MB x 64 2 Ranks -5 Symbol Typ. 940 1100 480 320 210 610 690 1140 1140 360 16 2020 Max. 1150 1310 580 450 290 720 860 1390 1470 450 17.6 2430 mA mA mA mA mA mA mA mA mA mA mA mA
3) 4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Unit
Note1)2)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx [component] + n x IDD3N [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx [component]
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TABLE 12
IDD Specification for HYS64D64020[G/H]BDL-6-C
Product Type Organization HYS64D64020GBDL-6--C HYS64D64020HBDL-6-C 512MB x 64 2 Ranks -6 Symbol Typ. 810 930 400 270 180 510 580 970 1010 300 16 1730 Max. 960 1120 480 380 240 610 720 1160 1240 380 17.6 2080 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Unit
Note1)2)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx [component] + n x IDD3N [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx [component]
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TABLE 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol -5 DDR400B Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.5 0.55 8 12 12 0.55 -6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 Max. +0.7 0.55 12 12 12 0.55 ns
2)3)4)5)
Unit Note1) / Test Condition
tAC tCH tCK
-0.5 0.45 5 6 7.5
tCK
ns ns ns
2)3)4)5)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (DQS and associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write cycle)
tCL tDAL tDH tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS tDSH
0.45 (tWR/tCK)+(tRP/tCK) 0.4 1.75 -0.6 0.35 -- 0.72 0.4 0.2 0.2 Min. (tCL, tCH) -- 0.6 0.7
tCK tCK
ns ns ns
-- -- +0.6 -- +0.40 1.25 -- -- --
0.45 1.75 -0.6 0.35 -- 0.75 0.45 0.2 0.2 Min. (tCL, tCH)
-- -- +0.6 -- +0.40 1.25 -- -- --
2)3)4)5) 2)3)4)5)6)
2)3)4)5)
tCK
ns
2)3)4)5)
TFBGA
2)3)4)5) 2)3)4)5)
tCK
ns
2)3)4)5) 2)3)4)5)
tCK tCK
ns
DQS falling edge to CK setup time tDSS (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time
2)3)4)5)
tHP tHZ tIH
2)3)4)5) 2)3)4)5)7)
+0.7 -- -- --
-0.7 0.75 0.8 2.2
+0.7 -- -- --
ns ns ns ns
Fast slew rate
3)4)5)6)8)
Slow slew rate3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse width (each input)
tIPW
2.2
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Parameter
Symbol
-5 DDR400B Min. Max. -- -- +0.7 --
-6 DDR333 Min. 0.75 0.8 -0.7 2 Max. -- -- +0.7 --
Unit Note1) / Test Condition
Address and control input setup time
tIS
0.6 0.7
ns ns ns
Fast slew rate3)4)5)6)8) Slow slew rate3)4)5)6)8)
2)3)4)5)7)
Data-out low-impedance time from CK/CK
tLZ
-0.7 2
Mode register set command cycle tMRD time DQ/DQS output hold time Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay
tCK
ns
2)3)4)5)
tQH tQHS tRAP tRAS tRC
tHP - tQHS
-- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- --
tHP - tQHS
-- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 -- -- --
2)3)4)5)
ns ns ns ns ns s ns ns
TFBGA2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD
40 55 15 -- 65 15 0.9 0.40 10 0.25 0 0.40 15 2 75
tRCD
42 60 18 -- 72 18 0.9 0.40 12 0.25 0 0.40 15 1 75
tRCD Average Periodic Refresh Interval tREFI Auto-refresh to Active/AutotRFC
refresh command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay Exit self-refresh to non-read command Precharge command period
2)3)4)5) 2)3)4)5)10) 2)3)4)5)
tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tXSNR
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK tCK
ns
tCK
ns
2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5) 2)3)4)5)
tCK
ns
tCK
ns
2)3)4)5)
2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac).
2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- tCK 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400)
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 14 "SPD Codes for HYS64D64020HBDL-5-C and HYS64D64020GBDL-5-C" on Page 22 * Table 15 "SPD Codes for HYS64D64020HBDL-6-C and HYS64D64020GBDL-6-C" on Page 25
TABLE 14
SPD Codes for HYS64D64020HBDL-5-C and HYS64D64020GBDL-5-C
Product Type Organization HYS64D64020GBDL-5-C 512MB x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
2 2
HYS64D64020HBDL-5-C 512MB x64 2 Ranks (x8) PC3200S-30331 Rev. 1.0 HEX 80 08 07 0D 0A 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02
PC3200S-30331 Rev. 1.0 HEX 80 08 07 0D 0A 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 01 02
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Product Type Organization
HYS64D64020GBDL-5-C 512MB x64 2 Ranks (x8)
HYS64D64020HBDL-5-C 512MB x64 2 Ranks (x8) PC3200S-30331 Rev. 1.0 HEX 20 C1 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 0F 7F 7F 7F 7F 7F 51 00
Label Code JEDEC SPD Revision Byte# 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 Description DIMM Attributes Component Attributes
PC3200S-30331 Rev. 1.0 HEX 20 C1 60 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 0F 7F 7F 7F 7F 7F 51 00
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax-0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
Not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
Not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7)
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Product Type Organization
HYS64D64020GBDL-5-C 512MB x64 2 Ranks (x8)
HYS64D64020HBDL-5-C 512MB x64 2 Ranks (x8) PC3200S-30331 Rev. 1.0 HEX 00 xx 36 34 44 36 34 30 32 30 48 42 44 4C 35 43 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC3200S-30331 Rev. 1.0 HEX 00 xx 36 34 44 36 34 30 32 30 47 42 44 4C 35 43 20 20 20 20 1x xx xx xx xx 00
99 - 127 Not used
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
TABLE 15
SPD Codes for HYS64D64020HBDL-6-C and HYS64D64020GBDL-6-C
Product Type Organization HYS64D64020GBDL-6-C 512MB x64 2 Ranks (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in E PROM Total number of Bytes in E PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels
2 2
HYS64D64020HBDL-6-C 512MB x64 2 Ranks (x8) PC2700S-25330 Rev. 0.0 HEX 80 08 07 0D 0A 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 70 00 00 48 30 48
PC2700S-25330 Rev. 0.0 HEX 80 08 07 0D 0A 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 C1 75 70 00 00 48 30 48
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns]
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Internet Data Sheet
HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Product Type Organization
HYS64D64020GBDL-6-C 512MB x64 2 Ranks (x8)
HYS64D64020HBDL-6-C 512MB x64 2 Ranks (x8) PC2700S-25330 Rev. 0.0 HEX 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 F8 7F 7F 7F 7F 7F 51 00 00 xx 36 34 44 36 34 30 32
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Description
PC2700S-25330 Rev. 0.0 HEX 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 F8 7F 7F 7F 7F 7F 51 00 00 xx 36 34 44 36 34 30 32
tRASmin [ns]
Module Density per Rank
tAS, tCS [ns] tAH, tCH [ns] tDS [ns] tDH [ns]
Not used
tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns]
Not used DIMM PCB Height Not used SPD Revision Checksum of Byte 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7
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Internet Data Sheet
HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Product Type Organization
HYS64D64020GBDL-6-C 512MB x64 2 Ranks (x8)
HYS64D64020HBDL-6-C 512MB x64 2 Ranks (x8) PC2700S-25330 Rev. 0.0 HEX 30 48 42 44 4C 36 43 20 20 20 20 1x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2700S-25330 Rev. 0.0 HEX 30 47 42 44 4C 36 43 20 20 20 20 1x xx xx xx xx 00
99 - 127 Not used
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
5
Package Outlines
FIGURE 2
Package Outline SO-DIMM L-DIM-200-22
67.6 3.8 MAX.
This chapter contains the package outlines of the products.
63.6 0.1
1.8 0.05
4 0.1
(2.15)
1
18.45 0.1 1.8 0.1
(2.4)
(2.45)
199
31.75
10.1
0.15
11.4 0.1
47.4 0.1
(2.7) (2.45)
1.5 0.1 10.1
2
(2.15)
4 0.1
200
6 0.1 20 0.1
2 MIN.
Detail of contacts
0.25 -0.18
0.45 0.03 0.6 0.1 Burnished, no burr allowed
GLD09573
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HYS64D64020[H/G]BDL-[5/6]-C Small Outline DDR SDRAM Modules
Table of Contents
1 1.1 1.2 2 3 3.1 3.2 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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